@User I was extracting some of the mpw4 submission and had a question about hierarchical connectivity.

slot-037

is the skull inverter. The inverter input is

A

and has an

li

pin. However, the parent hierarchy does not connect with

li

but rather drops

mcon

directly on the pin. The actual layout should be connected, but the extracted netlist does not appear to be.

.subckt skullfet_inverter Y A VPWR VGND
X0 Y A VPWR VPWR sky130_fd_pr__pfet_01v8 ad=6.2694e+12p pd=2.664e+07u as=4.4307e+12p ps=1.09e+07u w=4.05e+06u l=400000u
X1 VGND A Y VGND sky130_fd_pr__nfet_01v8 ad=4.2687e+12p pd=1.082e+07u as=6.4314e+12p ps=2.672e+07u w=4.05e+06u l=400000u
.ends

.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
...
Xskullfet_inverter_0 io_analog[1] skullfet_inverter_0/A vdda1_uq1 vssa1_uq1 skullfet_inverter
.ends

@User

Your screenshot is from skullfet_inverter_xl. Take a look at the connection from

io_analog[0]

.

You're absolutely correct. Sorry for the confusion. skull_inverter input is missing the via to met2 and that's what's causing the error.