@User FPGA tools enable me to view schematic representation of synth RTL. Are you aware if this is something xschem can show using .spice files output from the flow combined with the sym and model files from pdk libs?
James A
12/17/2020, 7:27 AM
My interest, here, is in viewing the "final" design with particular focus on post-CTS to check the buffers because the design splits clock source from loads due to the macro partition.