I am currently letting my interns develop an autom...
# shuttle
p
I am currently letting my interns develop an automated way to generate test structures, and also to generate test-patterns, in the hope that this will make characterization easier: https://docs.google.com/document/d/17zydtxUKJ8xkYFnlqlRr7mw4horNTw9C_LWG2jSx340/edit
t
Can you support things like testing inductors with this?
p
We could try. I have no idea about the requirements of inductors or the analog side of things.
This is the repository of my intern, but we it is still under development: https://github.com/1Kartikgupta/test_wafer_generator
So my planned interface is to have structures that should be tested generated and represented as MAGIC .mag files. Then our test-wafer generator will first add test-pads around the structures and connect them automatically, and then my demoboard tool will put many test-structures on a wafer
So if you want to test many variants of such inductors you could generate them (perhaps with the parametric cells in TCL in magic for SKY130) and then use our test-wafer-generator (when it is working) to add the test-pads and to put it on a wafer
c
If you want to probe stuff, then I think we might be benefit from the ability to alter the redistribution layer, to leave off solder bumps and redistribution metal and polyimide over the test pads. It is possible to remove the polyimide afterwards (we found out the hard way when we got some plastic packaged parts with polyimide and redistribution layer inductors decapped for probing...) but that needs nasty chemicals so would be easier if avoided in the first place. For some things like DC characteristics of transistors, we could mux out Kelvin force/sense connections from many different devices to 4 solder bumps, but the mux solution would only be ok where we are not testing for very low currents or at very high voltages. For things like measuring the real breakdown voltage of different p-n junctions, probe pads seem like the best option to me.
@Troy Benjegerdes I once had some inductors characterised with microwave probes. Based on that experience I strongly suspect that we can model the inductor with a field solver more accurately than we could measure it with e.g. Cascade GSG probes. (BTW I found nice photos of the probes on https://www.microwaves101.com/encyclopedias/rf-probing) Where required, my preferred approach for measurement is to build a LC oscillator on chip and measure the DC current that just makes it start oscillating and check that against simulation models, and tweak the models if required. (No RF probes.)
t
I like the idea of on-chip probing/testing/etc. I'd like to see an open gigasample/sec ADC at some point and if we can build that and connect it to a LC oscillator on chip that's probably going to be more accurate than probing, and then I have something to build a scope with 😉
c
It is easy to detect when a VCO starts oscillating with a spectrum analyser. It will leak out of every pin on the chip at about -50dBm, or a bit lower if you have shielded it very carefully. It will get into everything even if you don't want it to! For building a scope, I am hoping to avoid fast ADCs because (a) disposing of gigabytes per second into memory is hard, and (b) I don't want to get bogged down in export control laws, designing circuits is much more fun. Maybe it would be easier and more legal to make a (non-real-time) sampling scope (working in the manner of a Tek 11801).
t
Can you point me to the relevant export control laws? In the case of software, it's generally (at least recently) been considered that software with public source code is generally not subject to export control in the same way as compiled binaries or physical chips.
c
I am not an expert in these laws, but at least for closed-source products I think that fast ADCs when implemented on a chip might be covered by section 3a001.a.5.a of https://www.bis.doc.gov/index.php/documents/regulations-docs/2334-ccl3-8/file For designers residing outside the USA, or inside the USA but without holding US citizenship, this might prevent the finished integrated circuits from being sent to the designer. Sections 3D... and 3E... seem to try to cover software and technology (perhaps layouts?) that are for devices in 3A..., but I don't know whether being open-source would confer any kind of immunity from these requirements, and it might depend on the country that the designer lives in, whether it is allowable to make the design freely available and/or send it to the fab. These classifications are somewhat ridiculous (e.g. for many years any functional GSM phone would contain a synthesizer that used to be covered, and even today, any decent stereo audio amplifier with a CD player would potentially be 3a225), but ridiculous as these rules are, governments seem to (selectively) take them seriously (when that inconveniences somebody they don't like). Fortunately my ADC experience is so limited that I would not be able to make anything covered by these regulations, and I will for now choose to avoid the other categories as there is enough fun stuff that is not covered. Still, it would be great to get an authoritative legal opinion about what we should steer clear of, and what is ok.