I have created a digital delay line in sky130. 70ps resolution and 32 taps. I think this cell is a little simple for it's own shuttle run. Is anyone interested in adding it to their design for characterization? https://github.com/jonpry/ItsDelayed

Hi Jon, that sounds interesting. I haven't taken the time yet to figure out the circuit topology. I couldn't see any schematic and I'm guessing the netlist is generated. An indicative pdf schematic might make it more interesting to lazy people like me. A digitally controlled delay line might be useful in a sampling oscilloscope front-end, where a fast comparator triggers when the input waveform crosses a threshold, and then after a programmable delay, a sample-and-hold captures one sample of the input signal, that could go to a slow ADC (e.g. on an external microcontroller if not yet available on this process). This could enable a multi-GHz bandwidth oscilloscope to be built (for repetitive signals only).

Yes things like that can be done. IMHO an interesting example is altera serdes hardware. By using variable phase shift of the recovered clock they are able to plot the eye diagram of the receiver. It is also useful for for DDR memories