Note: When I said "all digital I/O to the pads is in 1.8V logic", I meant all digital I/O to the pads on the core side, not the pad side. There are also high voltage connections to the digital pad that are pre-wired, as they do things like controlling power-down and sleep modes that we aren't supporting because they are largely meaningless in the context of an experimental chip like this. Also there are pad connections on the core side that connect directly to the pad. For analog I/O you can just connect directly to the pad and shut off all digital, both input and output, from the management side. If/when using analog connections, please be aware of the specific-purpose I/O used by the management area. If you don't care about these functions because they don't apply to your project and you won't need them (e.g., 2nd SPI flash controls), then you can use them as analog I/O. But certainly be aware that some of the user pins should be strictly avoided for analog use: The housekeeping SPI (these are the only way to access the chip and SPI flash for flash programming, so if you override them and are, say, driving the pin with an analog output, you can potentially brick the development board), and the UART (without which you cannot communicate between the management SoC and a host).

when you say 'brick the dev board' do we have any pcb design in progress?

Not currently being worked on, but we have an agreement with Ant Micro to do it.