Couple questions: 1. Is this the channel to discuss issues regarding caravel? (I didn't see a caravel channel.) 2. The

caravel/spi/lvs/chip_io.spice

top subcircuit

chip_io

has duplicate pins.

+ resetb resetb_core_h vccd1 vccd1 vccd1 vdda1 vdda1 vdda1 vddio vssa1 vssa1 vssa1
+ vssd1 vssd1 vssd1 vssio

The verilog pin definitions are

inout vddio,      // Common padframe/ESD supply
    inout vssio,      // Common padframe/ESD ground
    inout vccd,      // Common 1.8V supply
    inout vssd,      // Common digital ground
    inout vdda,      // Management analog 3.3V supply
    inout vssa,      // Management analog ground
    inout vdda1,      // User area 1 3.3V supply
    inout vdda2,      // User area 2 3.3V supply
    inout vssa1,      // User area 1 analog ground
    inout vssa2,      // User area 2 analog ground
    inout vccd1,      // User area 1 1.8V supply
    inout vccd2,      // User area 2 1.8V supply
    inout vssd1,      // User area 1 digital ground
    inout vssd2,      // User area 2 digital ground

3. Is there a spice/cdl netlist for DFFRAM?

1. I think so? (@Tim Edwards, right?) 2. I will investigate how this happened; thanks. 3. If you run

make DFFRAM

, you should be able to get all views of it, including a layout-extracted spice netlist. I already have runs for all the caravel modules (minus top-level routing), but it's in a private repo. @mkk: Can we make it public so that people can access the large files we can't push directly to GH?