ALI AHMED
11/20/2020, 4:52 PMMatt Venn
11/20/2020, 4:53 PMMatt Venn
11/20/2020, 4:53 PMMatt Venn
11/20/2020, 4:53 PMMatt Venn
11/20/2020, 4:54 PMMatt Venn
11/20/2020, 4:54 PMMatt Venn
11/20/2020, 4:54 PMMatt Venn
11/20/2020, 4:54 PMMatt Venn
11/20/2020, 4:55 PMMatt Venn
11/20/2020, 4:55 PMALI AHMED
11/20/2020, 5:09 PMALI AHMED
11/20/2020, 5:13 PMMatt Venn
11/20/2020, 5:18 PMALI AHMED
11/20/2020, 9:06 PMTim Edwards
11/20/2020, 10:51 PMTim Edwards
11/20/2020, 10:53 PMdrr
11/20/2020, 11:48 PMwhat I'm doing (which may well not be optimal) is using the logic analyser to reset the user project after gpios are configuredI'm doing something similar but didn't use the LA. The "secondary reset" is an extra bit in wishbone reg that the SoC clears once the GPIO is ready to use. My user project gets reset by
wb_rst
and doesn't do anything useful until that wishbone reg is cleared and GPIO is known to be in a usable stateMatt Venn
11/21/2020, 8:35 AMALI AHMED
11/21/2020, 8:51 AMMatt Venn
11/21/2020, 8:53 AMMatt Venn
11/21/2020, 8:53 AMALI AHMED
11/21/2020, 8:54 AMMatt Venn
11/21/2020, 8:55 AMMatt Venn
11/21/2020, 8:55 AMdrr
11/21/2020, 8:57 AMrelease
branch
https://github.com/efabless/caravel/pull/6ALI AHMED
11/21/2020, 9:24 AMALI AHMED
11/21/2020, 9:24 AMALI AHMED
11/21/2020, 3:03 PMwb_rst
and doesn't do anything useful until that wishbone reg is cleared and GPIO is known to be in a usable state....
@drr can you point me to wishbone reg , from where and how should i read it in my user project? definitely it will be different signal from wb_rst_i, as it reset with mgmt SoC.Matt Venn
11/21/2020, 3:08 PMMatt Venn
11/21/2020, 3:08 PM