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So guys i have another question, what is the best ...
# shuttle
a
So guys i have another question, what is the best way to connect clock and reset to user project? is better to used the same way as counter example project using wb_clk_i, wb_rst or should we do it on user_clock2 (directly from pad)? since for counter example it should be enabled from mgmt are and we need to configure it before using our own user wrapper? am i right or wrong? is rst always connected through wb_rst?
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m
that's what I've decided to do
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I think it's the simplest option
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if you do use user_clock2 then you will need to deal with CDC in any logic that interfaces with the cpu
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and yes I'm just taking the wishbone reset and using that as a reset in the user project
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it's worth trying the user_project simuations in caravel
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so you can see what signals go where
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also, you should know that all the gpio takes quite a few clocks to get configured
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image.png
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I don't think the timescale is configured correctly, but you can see it take a lot of clocks until something happens on the io
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a
Thanks, so it means that i need to get status of gpios in my user project are before going to any other command, actually i have another soc in user area but we are using tile link inside it. Should i need a wishbone protocol to connect with mgmt core for gpios ?
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@Zain Khan, @Roomi Naqvi
m
what I'm doing (which may well not be optimal) is using the logic analyser to reset the user project after gpios are configured
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a
Good, awesome.
t
@ALI AHMED: I should have weighed in on this earlier: I provided the clock and clock2 outputs in case you need an adjustible independent clock. If you are communicating with your project solely through the logic analyzer as is done in the example caravel user project, then you don't need them. I thought they might potentially be useful to somebody.
@ALI AHMED: Also, the reset provided to the user space is (a copy of) the reset to the SoC. So it's more for the user project to either reset along with the SoC, or to monitor the SoC and be aware of when it is in reset.
d
what I'm doing (which may well not be optimal) is using the logic analyser to reset the user project after gpios are configured
I'm doing something similar but didn't use the LA. The "secondary reset" is an extra bit in wishbone reg that the SoC clears once the GPIO is ready to use. My user project gets reset by 
wb_rst
and doesn't do anything useful until that wishbone reg is cleared and GPIO is known to be in a usable state
m
@Tim Edwards when you say 2 clocks, isn't one of them the wishbone clock? So there is only one external adjustable clock.
a
Are u guys having issue with rtl simulation of caravel with user project? It would be helpful if some one, who already did a simulation, can provide link to verilator simulation ... I want to see some pointers in mu simulation... @drr, @Matt Venn it would be great help... Regards...
m
Not anymore
What problems are you seeing?
a
I am starting simulation, just freezed our user level rtl, need a jump start for c aravel integerated simulation...
m
Check the existing simulation in caravel
There are 3 test benches for the example project
d
@ALI AHMED there's a PR to fix some issues in the existing testbenches on 
release
branch https://github.com/efabless/caravel/pull/6
a
Ok got it
Thanks guys
I'm doing something similar but didn't use the LA. The "secondary reset" is an extra bit in wishbone reg that the SoC clears once the GPIO is ready to use. My user project gets reset by 
wb_rst
 and doesn't do anything useful until that wishbone reg is cleared and GPIO is known to be in a usable state.... @drr can you point me to wishbone reg , from where and how should i read it in my user project? definitely it will be different signal from wb_rst_i, as it reset with mgmt SoC.
m
Look at the counter example
It uses all the interfaces
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