@User: The clock will default to (probably) 10MHz from off-chip, as I don't think I can get a single-ended CMOS signal across the pad at any higher frequency than that. If the all-digital PLL works right, then the clock can run at the highest frequency that the STA tools say the Caravel core will run at; Ahmed can tell you what the STA tools currently say about the maximum clock frequency, but it should land around 50MHz or so.

What's your confidence in the digital pll?

I have a high confidence in the functional operation of the digital PLL; it simulates in ngspice. But I am a veteran chip designer so I don't trust anything 100% until I've seen it working on silicon. What you should do with the serial circuit depends mostly on how much cycle-to-cycle jitter you can tolerate. The PLL operates by adding or subtracting discrete delay stages from a ring oscillator, so each clock period may vary by that much delay from the cycle before or after it (I'd have to look up my comments to recall what that unit delay is).

Interesting

Assuming that the PLL hits the target frequency of up to about 150 to 200 MHz, then the jitter gets divided down with the clock. But it will still be worse than a standard PLL.

Sorry I've not checked the pll out fully. What's the frequency range?

I've forgotten, myself. But I have to put the testbench files in the caravel repository, so I'll do that now, and confirm what I have in my notes.

@Tim Edwards thanks for the response. So it means the clock being received from the wishbone interface to the user project area would run at 10 MHz? I can then change my UART design to work on that frequency if that is the case.

@Hadir Khan: I would check with @jeffdi on the status of the demonstration/development board. The 10 MHz figure for the off-chip CMOS clock is just off the top of my head---a likely "safe" value. If users are designing to that number, then we need to make sure it's put down in the BOM for the circuit board as that value.

@Tim Edwards does your statement above about the 10mhz clock also mean that signals in and out of the gpios are going to be limited to <10mhz?

@Matt Venn: Without having built a chip and measured the frequency response of signals at the pad, it's hard to say. The signal amplitude will be fine at 10MHz and will be essentially gone at 100MHz. Where the bend in that low-pass response is, I don't know. Probably around 20-25MHz. The 10MHz clock is a "safe" value, as I said, guaranteed to be well below any lowpass cutoff on the pads' frequency response.

ok, well I'll guess we'll find out!

@Tim Edwards is the frequency set for 10 MHz on the BOM? I need to finalise my uart configuration according to the frequency provided by the

wb_clk_i

that's what I've done