@User: See the testbench in

caravel/verilog/dv/caravel/mgmt_soc/uart/

. This only exercises

ser_tx

but the

ser_rx

line is easy to set up as an input. As you guessed, you would use GPIO_MODE_USER_STD_OUTPUT and GPIO_MODE_USER_STD_INPUT on GPIO 6 and 5, respectively, to switch those pins from the managment SoC UART to your own UART. Those two GPIO pins will be directly connected to an FTDI chip on the development/demonstration board, so they would be the ones you want to use. It will be a single-channel FTDI which is connected to the housekeeping SPI pins, so there will be jumpers to connect the Tx and Rx lines; then the host program needs to put the FTDI into serial mode. This is the default setup for an FTDI chip through the Linux driver. The UART baud rate will need to be set to be matched between the FTDI chip (which can set a variable baud rate over a large range with fine increments) and your circuit.

is there any more information about what pins are used by default?

The datasheet pinout is still correct on that I believe

thanks

@Matt Venn: My intention that the 2nd flash would have a footprint on the board but would be unpopulated.

great thanks!

@Tim Edwards by looking at the test you recommended, it is also setting the

reg_uart_clkdiv

since it is a tx pin. I wouldn't need to configure the same for

ser_rx

pin would I? since it would be connected to my Uart inside the user area which will have a uart receiver with a hardcoded baudrate and frequency that is equivalent to the

wb_clk_i

.

@Hadir Khan: Yes, the characteristics of any UART in your user project area will be entirely under your own control.

Which means I would just need to do a

reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT;

and then

reg_uart_enable = 1;

reg_mprj_xfer = 1;

while (reg_mprj_xfer == 1)