Thanks Matt. I'll reconsider partaking in the next 4 shuttles. The major flaw of this first shuttle is that you must use the Cravel harness which renders the 50 chips as useless, only suited for testing.of a small design. You can do a true test chip without a harness for less than 5000 euro at Europractice and Mosis (if you carefully pick the right process node). David Patterson and John Hennesey point out that a 100 test chips at 28 nm will cost around $14,000. That's less than half of the Efabless price.

You may well not be the target audience for this project. For me, the 50 chips aren't useless, but this is my first ASIC.

@Merik Voswinkel , having an open source pdk, open source eda is priceless.

Also the CPU is what, 20% of the project area at most? I suspect the range of projects that can't fit in the caravel harness but don't need a bigger die period is actually fairly narrow

the caravel project is really complex. time is short.

iiuc most of the complexity is around debugging support / being hard to brick userspace because you always have a manager(who speaks usb) to reset it