Okay, so as long as the openlane config files and testbench files know where the RTL is, it can exis...

Russell Friesenhahn

04/22/2021, 11:47 PM

Okay, so as long as the openlane config files and testbench files know where the RTL is, it can exist int he submodule and not necessarily in verilog/rtl, correct?

Manar Abdelatty

04/23/2021, 10:14 AM

@User yes, correct.

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