@User: I have incorporated three interrupt signals into the user project wrapper I/O. I should be able to make a nice testbench example with the example user project to have the counter trigger an interrupt and then have the processor sample the counter data. I still need to document all that.

Thanks Tim, a good start! Maybe we'll get multi-master Wishbone for MPW-3? There's so much useful IP that could use it. For example: DMA controller, high-speed interface controllers, etc...

Yeah that would be huge upgrade. I want fast memory access from user area