The link in the README of the caravel_user_project repo to the simulation details is 404. It links to: https://github.com/efabless/caravel_user_project/blob/main/docs/source/verilog/dv/README.md "For more information on setting up the simulation environment and the available testbenches for this sample project, refer to README."

Fixed now. It is supposed to link to this README https://github.com/efabless/caravel_user_project/blob/main/verilog/dv/README.md