open-source-silicon.dev

I can't use Icarus verilog for the simulation of my design due to the missing SystemVerilog support. Both the design as well as the testbench rely heavily on SV features, making it difficult even for GL simulation...
Therefore I thought about using Modelsim for the full-chip simulation. Will it still be accepted in a MWP submission?

For MPW-one efab wanted the tests reproducible. But I do not thing that was a strict requirement.

Are you running with `-g2012` in iverlog? We are mulling a switch to SV soon on our code base, but we are sticking to the supported subset in iverilog and yosys. A few syntactic niceties are missing, but it still seems to be a net benefit over verilog 2005. What SV features do you need that are missing?

The testbench makes use of packages, classes and functions which seems to not be supported by Icarus. A quick test resulted in multiple errors, also when using -g2012.
Rewriting the testbench would be no small task and is probably just the beginning...
It looks to be more straight forward to integrate the caravel testbench and use Modelsim.

Of course all simulation scripts and results will be available as well at the end.

It's not just SV. Icarus doesn't support parameterized macros!