Hello, I am having a question using openlane. I want to put macros in my design. So I use set ::env(EXTRA_LEFS) and set ::env(EXTRA_GDS_FILES) to read their gds and lefs files. But yosys does not recognize the error and I cannot pass the synthesis. In openroad-flow-script I just need to set ADDITIONAL_LIBS and ADDITIONAL_LEF. Is there similar variable in openlane?

You need to add your verilog files as the blackbox in VERILOG_FILES_BLACKBOX

What about memory? can the verilog for memory also be included?

Yes, you need the verilog file for memory in VERILOG_FILES_BLACKBOX.