Can anyone clarify me regarding the following information.
1. The submitted design is harnessed with caravel project user project area, which means the user design is a part of caravel SoC which consists the picorv32a processor and other peripherals ( along with the user design ref:
https://github.com/efabless/caravel)
2. Is the fabricated chip consists the caravel SoC (along with processor) or only the user design
3. In the example project config file which are parameters should not be changed like DIE area (0 0 900 600). (since the pl target density was mentioned only 0.05 can we change this configuration ref:
https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1634150627104800?thread_ts=1634104863.096100&cid=C017HPHCMEY)
4. The user project area was restricted with 38 GPIO but the example counter project consists multiple IO ports more than 38. Are we allowed to use more ports. (ex 20 bit adder need 2 input of 40 ports and 1 output port of 21 bits, as a total 61 IO ports. ref:
https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1634355866111300?thread_ts=1634355442.111000&cid=C017HPHCMEY)
5. Are we need to remove the unused input/output/power ports from user_project_wrapper.v or need to leave unconnected with same order.
6. For the digital design Is it enough to copy the design files to verilog directory of caravel or any other files (like gds lef def from openlane project folder) need to be copied to some other caravel directory to run make user_example_project.