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Someone, please help me to get rid of this issue I...
# shuttle
m
Someone, please help me to get rid of this issue I am facing this for the last two months, while running 
make user_project_wrapper
I am getting one LVS error, please help me to fix this error. 🙂🙂🙂
m
post a link to your repo
m
v
Have you tried with latest openlane version
m
i just updated yesterday
m
your gds and lef files of user_proj_example are very old compared to your configs
are they current in your local copy?
if not then that could be the problem
m
yes i have not upload them
m
if they are, then you should commit them also to the repo othewise when people look they have an inconsistent repo
m
would be ding in few minutes
m
you need to think how to make it easy for me to check for you
m
@User sir please have a look just updated everything, sorry for the delay
m
Copy code
Warning:  Ports "vssd2" and "vdda2" are electrically shorted.
Warning:  Ports "vssd2" and "vccd1" are electrically shorted.
From your extraction output.
m
@User any hint about how to fix it please 🙂
m
Do you have klayout?
m
Yes I have it
m
Open 
user_project_wrapper.gds
. From the extraction results, you can see that the short is detected at the top level. The trick is how to find it. klayout lets you find the shortest path between 2 nets. Do you know how to do that?
m
Unfortunately I don't know to use klayout but I will try to learn and fix
m
I think it's easier than that
here's your gds
image.png
met4 is used for power and is the vertical lines here
they should stop when they reach the edge of your macro
like this
image.png
but yours keep going through
so then you get this
image.png
where the met4 pdn smashes into existing met4 in your design, causing a short
👍 1
why that is happening I don't know
but one weird thing I noticed in your repo is that the symlinks in openlane are broken
I'm not sure if that's a real problem or just an artifact of you commiting everything in the repo
m
As @User pointed out, looks like you have 2 met4 shorts. vccd1 - vssd2 at x= 1199 and vccd1 - vdda2 at x=1503.
m
@User how do you find the shortest path between two nets in klayout? That is useful...
m
Tools -> Trace Net -> Trace Path Then you choose two nets. Follow the prompt at the bottom of the layout window. You have to choose a layer defined in the layer stack. (ie, pin layers won't work with the default configuration).
@User Looking at your 
user_project_example/config.tcl
file
Copy code
# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper)
# where the PDN is planned on metal 5. So, to avoid having shorts between routes
# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
set ::env(GLB_RT_MAXLAYER) 5
It says the maximum layer for routing should be metal 4, but you've specified metal 5. It warns that this will cause shorts, which is what you have. Can you set this to metal 4 and see what happens?
m
Fine sir I'll just check this and correct it
m
no, 5 is correct
because 1 is LI
so all the metal layers are +1
the problem we found in Mohammad's design was that the PDN wasn't stopping on layer 4,
m
@User Thanks for the correction. Although, I think they recently removed Li as a routing layer.
m
@User has the same problem
image.png
should be like this:
@User did you resolve this?
if not then I think you should open an issue on openlane about this. there is clearly some problem
m
@User @User Looks like the max routing variable has changed. old: 
set ::env(GLB_RT_MAXLAYER) 5
new: 
set ::env(RT_MAX_LAYER) "met4"
https://github.com/The-OpenROAD-Project/OpenLane/pull/795/commits/f45b6b5a9040e90a17ebfe64d9b0539a46317c1b
m
I will run with the modifications 😀
p
@User I changed the RT_MAX_LAYER to met4 for both user_proj_example and user_project_wrapper still the same error persists.
m
No it's not this, it's that the pdn isnt interrupted by the macros
I tried @User repo yesterday and got the same result. Then I tried replacing the caravel submodule with one from mine and got the same result
There is nothing in their config about pdn, so I don't know what can be causing it
p
@User The flow got completed without any fatal erros but there was short for vssd1 and vdda1
I changed the macro position to 900 1300
@User Do you know how to use GLB_RT_OBS? I am not getting what parameter should I pass to the variable
m
image.png
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