For shuttle is it compulsory to run full chip simu...
# shuttlep
Pranav Lulu
12/15/2021, 4:55 PMFor shuttle is it compulsory to run full chip simulation mentioned in the efabless document?
I was trying to run RTL & Gate level simulation but it gives an error.. I tried to use -I flag to give PDK_ROOT to iverilog but it gives an error..
m
Matt Venn
12/15/2021, 5:09 PMNo not compulsory but recommended
👍 1
Matt Venn
12/15/2021, 5:10 PMDefinitely do RTL SIM so you can check the top level wiring and your work functions inside the harness
👍 2
Matt Venn
12/15/2021, 5:11 PMFor GL I have been doing a normal sim for caravel and use the powered verilog for the dut
Matt Venn
12/15/2021, 5:11 PMThe GL takes too long for all of caravel
p
Pranav Lulu
12/15/2021, 5:14 PMHow to give PDK_PATH to iverilog using it's -I flag?
m
Matt Venn
12/15/2021, 5:15 PMWhy don't you use the existing makefiles?
Matt Venn
12/15/2021, 5:15 PMCopy and alter one of the ones in dv directory
p
Pranav Lulu
12/15/2021, 5:18 PMWhich makefiles? I was following the simulation flow mentioned on caravel official document. But when I make run for SIM=RTL it gives an error regarding the lib.ref
Pranav Lulu
12/15/2021, 5:19 PMI will post the screenshot of the error tomorrow so that it will be clear what I am trying to say 😅
m
Matt Venn
12/15/2021, 5:24 PMp
Pranav Lulu
12/15/2021, 5:38 PMThanks Matt 👍
2 Views