Is there a way/example to write to user area wishbone slave through C? I am just seeing these examples: https://github.com/efabless/caravel-lite/tree/c2943440e278814787f761585b99b9ea3c1f4121/verilog/dv/wb_utests Which instantiate certain modules to test wishbone.

@User: Per that page (which needs updating and needs a few typos corrected), you can see that the range 0x30000000 to 0x3fffffff is reserved for the user project area. The management SoC will apply a strobe signal (cyc and stb) to the user project area whenever the C program writes in that range. You can create a wishbone module in the user area that responds to addresses in that range. See in the

caravel_user_project

repository the testbench

verilog/dv/wb_port/wb_port.c

. The example project only defines one register which it references by the C definition found in caravel

verilog/dv/caravel/defs.h

defined as "`reg_mprj_slave`" (and is equal to address 0x30000000). The slave module verilog is defined in

caravel_user_project

at

verilog/rtl/user_proj_example.v

. It's rather overly-simple and doesn't even decode the address, so the single register is effectively mapped to every address in the range 0x30000000 to 0x3fffffff.

thanks

I made a video and a demo also: https://www.zerotoasiccourse.com/post/caravel-wishbone-demo/