Anyone Pls help to solve this error... Thanks

@User Maybe post your top gate level verilog.

This is an analog design

@User How are you setting your macro power connections? This might be related https://skywater-pdk.slack.com/archives/C016G7Z8GDR/p1640795235184400?thread_ts=1640693345.183700&cid=C016G7Z8GDR