Hi all, can someone that has passed a GL test share its link? Thank you very much

Any of the gate level verilog tests in the caravel repository should pass (e.g.,

caravel/verilog/dv/caravel/mgmt_soc/*/

). Have you tried running one of those?

To run a GL test for your user_project_wrapper, it needs to put all GL netlists of your hardened macros and user_project_wrapper module in verilog/gl. Then you need to update the verilog/rtl/uprj_netlists.v file to point to the GL netlist files. Finally, you create a testbench for your test case in verilog/dv/[testname]. To run the GL test, do `make SIM=GL' in the verilog/dv/[testname]. You can reference to this link https://github.com/phthinh/soric_project. It has a couple of GL tests for a RISC-V based SOC design, for example, verilog/dv/soric_mem_test for memory access test and verilog/dv/soric_simple_test for download and running a simple program through the Caravel system via Wishbone interface.