Please anyone help me on this

Just a guess, but looks like it's saying it can't. route to

mprj/io_in[37]

. Is it a port under an obsm* layer?

Perhaps two macros overlap so the io_in[37} pin of "mprj" is covered?

Search the run directory and see if you have an xml marker file for klayout. Then you can load the floorplan and see where the markers are. Post a screenshot of what you find

@User Could you add how you can load an XML marker file into klayout? In the window accessible under the Tools->Marker menu of KLayout, only .rve, .rve.gz, .db, db.gz, .lyrdb, .lyrdbgz files can be loaded, but XML files do not seem to be supported (for KLayout 0.26.2 up to today's KLayout version in its official GIT repository). According to https://github.com/efabless/mpw_precheck/blob/main/debug_precheck.md, the mpw-precheck tool should also generate .lyrdb files, but it looks like it also only produces XML marker files for DRC violations. The command line arguments given there to load a marker file with KLayout also don't seem to work.

@User I had same issue. It was caused by the pin being missaligned on 5nm grid. Also it happens if it is covered by macros.

not solved yet 😞

@User Can you check the layout to see why

mprj/io_in[37]

doesn't have an access point? If you can't because there's no layout. You could try temporarily removing the

mprj/io_in[37]

connection from the rtl, create the gds, and then check the location of the pin.

The def contains the pin.

Right, but the def was created from the rtl, correct?

@User How to check if the issue caused by the pin being misaligned on 5nm grid? @User We checked the pin, it is there on the macro, the lef has the relevant info about the pin as well and is being read. It is not making any sense at all.

Can you see the pin position in the lef/def? Is it a multiple of 5nm like the other pins? Do you have a def viewer?

I am using Klayout for viewing it.

Use text editor, and search for according pin

This is the pin in question

mprj/io_in[37]

. It's on the

user_proj_example

cell, not the

user_project_wrapper

, I think.

Yes, the error is in

user_proj_example

pin

io_in[37]

The screen shot appears to be

user_project_wrapper

not

user_proj_example

. Check the metal obs layers above and below. Can you post your lef/def somewhere?

You were not looking for overlaps. The purpose of opening it in editir, was to see if the pin was missaligned on manufacturing grid of 5nm. Are all coordinates divisble by 5 for that pin? If not, then it might be a reason for failure. There is other reasons for that too. For example it might have overlaps with other pins.

Yes, I have already seen that there is no overlap.