open-source-silicon.dev

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*<!channel>* Hello everyone,
We identified another issue that was blocking tapeouts from reporting correctly when successful.  The issue has been corrected and deployed to the platform.  If you had tapeouts with 0 DRC errors that were reporting as failed, please resubmit your tapeout job again and you should see the job report a success.
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Screenshot from 2022-03-12 20-50-06.png

Hi, I've tried again but I'm still seeing tapeout as reporting as failed with a suspicious klayout beol sigterm mentioned before looking through the outputs in open galaxy

web platform logs:
```
            [03/12/22 12:30:01 PST] FAILED
            STDOUT: {{Extracting Files}} Extracting compressed files
STDOUT: {{Project Type Info}} digital
STDOUT: {{Project GDS Info}} user_project_wrapper: 8b0d81482d29bfe35b3b6da5917e617c0912aa10
STDOUT: {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
STDOUT: {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
STDOUT: {{START}} Tapeout Started, the full logs can be found in u6289_gatecat/design/coriolis_test_soc_-_mpw5_vexriscv/jobs/tapeout/3b14450f-1ae4-4447-ac45-d0a243dc015c/logs
STDOUT: {{Step Update}} Generating Final Layout: Step 1 of 7
STDOUT: {{Step Update}} Generating Final Layout: Step 2 of 7
STDOUT: {{Step Update}} Generating Final Layout: Step 3 of 7
STDOUT: {{Step Update}} Generating Final Layout: Step 4 of 7
STDOUT: {{Step Update}} Generating Final Layout: Step 5 of 7
STDOUT: {{Step Update}} Generating Final Layout: Step 6 of 7
STDOUT: {{Step Update}} Generating Final Layout: Step 7 of 7
STDOUT: GDSII File [caravel_0005d159.gds] sha1sum: f59564e3e6e182c3c77fa75ef898c105b060a787
STDOUT: {{Step Update}} Converting Final Layout: GDSII -&gt; OASIS
STDOUT: OASIS File [caravel_0005d159.oas] sha1sum: 4d5e95346f1a4779224b5554205c74fe03790530
STDOUT: {{Step Update}} Executing Check 1 of 5: Klayout Missing Cells on [caravel_0005d159.oas]
STDERR: [ WARN ] Missing Cells Check Result: 'caravel_0005d159.oas' has 0 missing cells.
STDOUT: {{Step Update}} Executing Check 2 of 5: Klayout Front End Of Line on [caravel_0005d159.oas]
STDERR: [ WARN ] FEOL Check Result: 'caravel_0005d159.oas' has 0 DRC violations.
STDOUT: {{Step Update}} Executing Check 3 of 5: Klayout Back End Of Line on [caravel_0005d159.oas]
STDOUT: {{Step Update}} Executing Check 4 of 5: Klayout Metal Minimum Clear Area Density on [caravel_0005d159.oas]
STDERR: [ WARN ] MET Density Check Result: 'caravel_0005d159.oas' has 0 DRC violations.
STDOUT: {{Step Update}} Executing Check 5 of 5: Klayout Field Oxide Mask Density on [caravel_0005d159.oas]
STDERR: [ WARN ] FOM Density Check Result: 'caravel_0005d159.oas' has 0 DRC violations.
STDOUT: {{FINISH}} Executing Finished, the full logs can be found in u6289_gatecat/design/coriolis_test_soc_-_mpw5_vexriscv/jobs/tapeout/3b14450f-1ae4-4447-ac45-d0a243dc015c/logs```

just wondering if you managed to track this down at all? if not I'll try a smaller SoC config

I've tried a smaller config (reduced cache size) and that passes tapeout fine, in the worst case that will do for MPW5