Also, is there any difference between the pins for the user_analog_project wrapper (vcc, gpio_analog, io, clock)? It seems on the magic layout they are just pins on metal layers with nothing connected, so we could wire them to anything?

@User do you know about this?

All pins on the wrapper are connected out to the Caravan chip. Of course the wrapper just shows a stub of metal; that's why it's called a wrapper. It just shows where you need to connect things.

@User I guess I'm confused as to what are the differences between the analog wrapper and the digital one. I was under the impression that the analog wrapper was mostly empty as opposed to the digital one? so in this diagram for the digital wrapper, the orange in the user_project_wrapper is the free space available whereas in the analog wrapper, the entire wrapper space is available? but both will need to fit onto the vanilla caravel chip?

You are looking at a user project wrapper that is already populated with a user project. Both wrappers are initially empty and can take up the whole 10mm^2 user area.

@User and both will have 38 IO ports and 4 power pads? Is there a difference between gpio_analog and io_output pins? I see both are used in the xschem example (for the analog wrapper with the example_por) but adding up the numbers it seems to be 27 IO ports and not 38

The best reference for the I/O mapping is in the caravel_user_project_analog repository under

verilog/rtl/user_analog_proj_example

. The Caravan chip removes 11 GPIO pads from the top of the chip and replaces them with bare pads for connecting things like high voltage or high frequency analog signals. That's why the count of GPIO pads gets reduced from 38 to 27. The

gpio_analog

signals are for connecting analog signals to the GPIO pads (not the bare pads). Since those signals connect to what are also digital-capable pads, they are limited to 0-50MHz range and 0-3.3V. Also, because analog signals can interfere with digital functions, there are certain pins (mainly those used by the housekeeping SPI) which are not allowed to have

gpio_analog

connections. The

io_analog

signals are the ones that go to the bare pads.

@User sorry for all the follow-up questions, but just to make sure I am understanding correctly from the verilog/rtl/user_analog_proj file, there are 1. 27 GPIO pins which go through the GPIO block before going to the bare pads. 2. 10 io_analog pins which connect to the bare pads/pinout? Thanks for all your help!

Yes I'm pretty sure that is the case, but 11 bare pads as @User says above

@User: By definition, a "bare pad" is one that isn't connected to any driver circuitry, so I would call it 27 GPIO pads and 11 bare pads, but yes, I think you have the understanding correct.

Okay, sounds good. Thanks @User and @User for all the help!