Hello, during connectivity check, I have observed ...
# cadence-innovus
w
Hello, during connectivity check, I have observed the that nwell are not connected to VPWR. @User @User Any ideas?
n
@Wajeh ul hasan I don’t know how to fix it in Innovus, I guess that there is no information/layers for n/pwell connections (VPB/VNB) as Innovus work with abstract view (from li to metal 5 only). But those pins can be physically connected via tap cells (sky130_fd_sc_hd__tapvpwrvgnd_1) as @Tim Edwards mentioned above. I don’t see that error in Klayout with full DRC check when using the tap cell.
t
I was not aware that Innovus would do the connectivity checks this way; currently the technology LEF file does not define a cut layer from nwell or pwell to local interconnect, and so the contact isn't represented in the abstract view. I don't know why they would do connectivity checks with abstract views instead of with GDS views, but whatever.
w
So, the only way this issue is going to go away is to define a cut layer from nwell or pwell to local interconnect in the technology LEF. Is it going to be added in the near future. Or any suggestions to add it manually? @User
n
How about remove both VNB/VPB pins in LEF file as we don’t use those pins in digital designs?
t
@Wajeh ul hasan: It's more than just adding the cut layer to the technology LEF, because the connectivity in the layout will not be found unless the cut layer appears in the tap cells. So the cuts will have to be added to the tap cell abstract views.
@Nguyen Dao: That would just create more problems. I think the better solution would be to ignore the ERC checks from Innovus and let the DRC latchup deck checks take care of that.
w
@Tim Edwards Makes sense, thanks