@User: (1a) The pad cell abstract view shows errors because the pins are shorter than the minimum width of the top metal layer. This may have been done on purpose; it means that the cell will always show an error until it is properly abutted to another pad. Then the combined width of the two pins will exceed the minimum metal5 width and the error will disappear. (1b) The full view of the HD cell is showing an error that I had not seen before and was not aware of; SkyWater allows tighter rules on the source and drain of MOSFETs inside a standard cell. The rule documentation made it sound as if only the standard pFET and nFET followed that rule, and in a handful of standard cells I checked, the HVT pFETs did not have the tighter spacing. But the A1 pin here clearly does, so it looks like I will have to identify all types of FETs inside the standard cells and treat them specially, which is a pain, but oh, well. Thanks for bringing it to my attention. (2) The I/O pad with "hardly anything" is an unexpanded cell. Use "expand" to see all the contents. (3) N-well taps are "nsubstratencontact" or "nsc" for short, and P-substrate contacts are "psubstratepcontact" or "psc" for short. (4) The SkyWater standard cells have a special "tap" cell in each library that contains the taps to well and substrate. You are supposed to array them throughout a standard cell layout such that they are always within 15um of any diffusion (the rule is considerably more complicated than that, but that's the general rule of thumb). If you are using openlane place and route, this will be done automatically.

Thanks for clarification