I have created NOR gate layout using fingers ,on extracting ..it is showing incorrect nodes(drain and source swapped) for nfet inside white box in below image. Any mistakes in layout desinging using fingers?

@Deepak For normal cmos processes, I believe the source and drain are interchangeable. The extraction routines can't tell the difference, so the comparison routines are ok with either source or drain connections.

LVS has the option of permuting source and drains so that you can still get a match