open-source-silicon.dev

project 0 - seven_segment_seconds: <https://github.com/mattvenn/seven-segment-seconds/tree/ee4edebb53bbee8ad2664439dd7564eb441e680b>

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project 1 - ws2812 : <https://github.com/mattvenn/ws2812-core/tree/a737601323154a2a6b6c9dc70c4095352f3259af>

project 3 - vgaclock : <https://github.com/mattvenn/vga-clock/tree/master>

project 4 - spinet <https://github.com/millerresearch/spinet/tree/master>

project 5- freq cnt: <https://git.sr.ht/~jersey99/asicfreq>

lvs errors already reported  here: <https://github.com/RTimothyEdwards/netgen/issues/7>

So apart from the LVS error they are all the same: All nwells must contain metal-connected N+ taps (nwell.4)

My understanding was that those are false positives

yeah, was just talking to <@U016HSALFAN> and he suggested posting them here anyway

Are you running DRC on the GDS or on the DEF ?

these reports are from runs/xxxx/logs/magic/magic.drc

Not really.  Do you set `::env(MAGIC_DRC_USE_GDS)`  ?

ok, then it's on the GDS.  (Default is `1` )

<@U0172QZ342D> Looks like the LVS error might be similar to the one in zipdiv. It appears to be a buffer discrepancy, but it may be something that does not make a significant difference in the final design. There was some discussion on <#C017UA7LEUV|verification-be>
<https://skywater-pdk.slack.com/archives/C017UA7LEUV/p1605706697015700>
<@U016HSALFAN> says he's not getting the error in rc5 (develop).

<@U0172QZ342D> <@U016HU5HK8V> Quick check. `MAGIC_DRC_USE_GDS` is used in the `openlane/scripts/magic_drc.tcl`. Is this the standalone DRC script?
I think the `openlane/flow.tcl` script calls `run_magic_drc` which is `located in scripts/tcl_commands/magic.tcl` and only uses the `maglef` views, AFAICT.

`run_magic_drc` from  `scripts/tcl_commands/magic.tcl`  invokes `magic` and tells it to run `scripts/magic_drc.tcl`

<@U016HU5HK8V> Thanks for the quick response.
So when `MAGIC_DRC_USE_GDS` is set, the `set ::env(MAGTYPE) maglef` line in `scripts/tcl_commands/magic.tcl` effectively doesn't do anything?