Hi @User, as I mentioned over in #sky130 I was looking at doing detailed RC extraction on the standard cells (specifically an X12 inverter from the fd_sc_hd kit as a trial). I mainly followed the circuit extraction tutorial #8 on magic's webpage (http://opencircuitdesign.com/magic/tutorials/tut8.html) to come up with the magic script (first screenshot). When I invoke magic I am also passing the sky130A.magicrc from open_pdks. There are 2 main issues that I am currently having (I've also attached the .spice file being extracted in case that comes in handy): First issue is the body pins of the extract FETs are being assigned to a new net called "error" and that error is extracted as a new port in the subckt as seen in the second screenshot. If I skip the 

extresist

 step then these pins are extracted correctly. It seems this might have to do with the limitations of substrates and the .sim format and I just need to regex correct these nets? The other issue is with the extract capacitance, it looks like for the most part I just have lumped capacitance between the original nets (ie. the ports in the subckt A, Y, VPWR, VGND, VNB, VPB). There is an exception though, where there seems to be a distributed capacitance model for some of the nets and the n-substrate VNB. Specifically, there are capacitors between A@<->VNB (ie. each of the A net wire segments and the n-substrate), Y@<->VNB and VPWR@<->VNB. I found it interesting that all of these distributed model capacitors are to VNB, and also that there is still, what seems to be, a lumped capacitor between these nets (ie. a somewhat large capacitance between A<->VNB, Y<->VNB and VPWR<->VNB... much larger capacitor than any of the distributed capacitors). Ideally I could extract distributed capacitance for all of the nets, but I am also worried that something more fundamental might be going wrong, I was wondering if you have seen this or have any suggestions?

Short answer to the middle paragraph: Yes, the "error" nets are the substrate, because the .sim format does not represent the substrate or transistor bulk connections in any way. You will need to repair those manually or by script.

Thanks for the advice @Tim Edwards, I'll give those suggestions a shot, really appreciate the feedback!