The wiring tool interacts weirdly with generated transistors. Normally when I click on a metal rectangle the wiring tool starts a route with width equal to the width of the short side. When I click on a rectangle that is part of a generated nmos/pmos the wiring tool starts out as a 12 unit width (I think thats the min width) and is not centered on the rectangle. Is there any way around this?

It may be because there are contacts there, which are not drawn because you're omitting layers, but which are interfering with the way magic determines how big to draw the wire. What I usually do when magic won't automatically start a wire is either to place an initial rectangle and paint it by hand, then run the wire tool off of that; or, equivalently, use the "fill" command (e.g., "fill n m1" for the example screenshot above) to do the same.

Yah, its doing the distance between m1 edge and vialocali

Yes, what you want is definitely a nice-to-have feature, but I don't think that it's trivial to implement, because it's depending on a "select" command that selects the largest area of a single material, and there isn't an option on that command to select the largest area of visible material only, or more to the point, the largest area of metal while ignoring contacts.