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I'm confused by a DRC error and I don't quite get what the message means. I'd appreciate any help :slightly_smiling_face: . I'm going to try to include pictures in a thread under this message.

image.png

The following 9 transistors were made by first placing 1 transistor down, and then using the `array xlo xhi ylo yhi` command. I made the box have at least 2um spacing around the transistor cell edges.

I get a DRC issue here. When I select the instance of the array and run `drc why` it reads `This layer can't abut or partially overlap between array elements`

I retried the `array` method, but now with much larger spacings and I don't get any drc issues (image below). Here's the thing though. I placed a new transistor _much closer_ than any other array and I get no drc errors when I select the area or instance of the new, individual transistor.

From that it makes me think I'm either not using the `array` command correctly, or I'm disregarding an actual DRC rule which I just can't see. Any help on this would be appreciated :)

I'm not sure what's going on and I can't reproduce it.  Can you post the .mag file of the example with errors (or rather files, because there will be two of them, one for the device, and the top level)?

currentMirror.mag

sky130_fd_pr__pfet_01v8_lvt_HSEZKA.mag

<@U01N2MWV2JZ>:  It seems that you have uncovered some bug.  It looks like some kind of scaling issue, since the error area looks similar in size to the layout but is offset down and to the left.  I'll debug this, but if you aren't doing too many of these, you might want to just make one instance, select it, and do "copy e 9um" so that you get N individual instances instead of an array of N instances.  Whatever the bug is, I'm sure it's related to arrays, and some changes I made to the way DRC is done (such changes tend to get less well tested on subcell arrays).

I tracked down the bug, and it is one of those strange things where the code appears to have been in error forever (predating my work on it) but nobody seems to have noticed, and I'm not really sure why it doesn't show up more often.  Fixing it may actually improve the DRC performance on arrays (but probably not significantly).  I just pushed a fix to <http://opencircuitdesign.com|opencircuitdesign.com> (github updates overnight).