I figured I should move talk of the extraction to the channel for Magic itself. @User I have an example of the provided workflow generating a netlist with invalid connectivity when I try to extract resistances.

Actually it's good to know that the problem looks more trivial than it originally seemed. Please post a tarball of the example (or email it to me), and I can use that to debug.

Thanks, I'll take a look at it.

I started routing my lowest bandwidth circuit first so I have time to learn. This is just my low frequency error amplifier.

Yes, that's right. It's already the gate voltage, so you're just lowering the resistance from one side of the transistor to the other. But okay; I assumed that this was high frequency since your system is high frequency. If you don't strap across the gates, you can just remove the bottom side contact.

I am using a script to generate the FETs and place them on grid before routing. The other side gate contacts are unused, but no easy way to remove them. Its a layout optimization vs time spent thing

Another (unsolicited!) pointer: Watch out for the very high resistance of local interconnect. It is actually a DRC error to have an uncontacted length of local interconnect with an aspect ratio of > 10:1. However, magic can't check that rule (neither, for that matter, can Calibre).

I think next version of my script I am going to have it extent the gate / drain contact connections to my routing grid spacing.

I fixed the bug in magic---it was caused by a lack of checking for labels with zero-area geometry. "out" was a zero-width line, and so it just lost track of it (tried to do an area search over the label area and failed to find anything, of course). I pushed the fix to the master branch on opencircuitdesign.com (github mirror will update overnight). I noticed when I re-ran that I got a number of "missing gate" errors that I don't remember being there before. Anyway, previously the node "out.n7" was at the position of the label, and now "out.n7" is gone and has been replaced by "out", so that much looks correct to me.

Sweet! Thanks a lot!

I have no idea. Didn't seem to be an issue, so if you can simulate off the netlist that is being produced, then I will treat it as a false positive rather than a true bug.