This is my stupid little opamp so far. I drew the transistors and miller cap according to my spice simulation but I'm having trouble with connecting everything. How do I figure out which layer the contacts are on and what they connect to? I guess I'll want to insert various vias to local interconnect and metal layers and draw routes on them, but... how do I figure out which layers to use? Another thing I'm not quite sure how to do is connect the wells correctly. This is a g5v0d10v5 device, so need to make sure the pfet bulk is... not 1.8v. Also have a few where bulk is not a supply so as far as I understand I need to draw a deep n/pwell under those.

(1) You should make use of the options within the parameterized cells to connect up to metal1; you don't want to route in local interconnect because of the high resistance. (2) Cluster your N devices together and your P devices together; for devices that should be matched, consider merging them into one layout device and adding dummy transistors on each side. (3) Make use of the "+" and "-" prefixes on the via coverage in the parameterized device for source and drain; e.g. source = "+40" coverage and drain = "-40" coverage. That shifts the via contacts to the top and bottom (e.g., at the bottom of the source and at the top of the drain) and allows you to connect across the devices with a horizontal metal1 stripe. (4) A pFET well can be connected locally; the nFET substrate must be ground or else a p-well in a deep nwell structure. There is an item in the Devices menu to draw a deep nwell structure. (5) Take a look at the power-on-reset layout in the Caravel repository for a similar example that has a handful of parameterized devices, including transistors and a capacitor.

I think I have the via options selected. It's just hard for me to tell visually what's going on with the layers. For example, I have no idea what layers I need to use to wire up to mim capacitor, or which layers I'd need to connect the pwell to the source. Making matched devices into a single layout device makes sense, but why group nmos and pmos? Seems like that would give weird routing. Can you edit the parameters of an existing cell, or you need to create a new one?

Generally it is considered better to have all the transisistors arrayed in similar environs, which will improve matching, and the wiring can be crazy as long as you are not, say, crossing wires where coupling matters. The MiM capacitor connects metal3 (bottom) to metal4 (top), but it's not a good practice to wire out from the bottom plate directly, so the contact on the side connects the bottom plate up to metal4. So you connect metal4 to the center region of the MiM (cap top) and to the contact on the side (cap bottom). Connect pwell or well to source with metal1. You can use local interconnect, but it's better to keep the local interconnect geometry the same on all devices, again for matching. The further up you go in metal layers, the less impact it has on matching. And yes, you can edit parameters of an existing cell. Just select the cell ("i" key) and type "Ctrl-P" to bring up the parameter edit window.

thanks