<@U017UPJEGKZ> i have the same DRC check error for...
# magicm
Manh Tran
06/02/2021, 5:11 PM@User i have the same DRC check error for my design. I layout my analog circuit and i need a sealring for this design. But, when i use sealring that generate by magic, it have a DRC error like that: "Deep N-well spacing to N-well < 4.5um (nwell.7)".
I think, in my layout, the Nwell is on the Deep N well, that is no DRC error for the example. So i don't know how to solve this problem. And how can i verify exactly my layout before pass Efablesss ( or Skywater) check. This problem is critical or not?
Thank you, and have a nice day ! 🙂
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Weston Braun
06/02/2021, 5:54 PMThe deep N-well spacing to N-well is for unrelated (unconnected) nwells
Weston Braun
06/02/2021, 5:54 PMI am a bit confused, your design appears to have a DRC error you are trying to clear?
Weston Braun
06/02/2021, 5:57 PMYour color scheme seems a bit different than mine, but it seems you might have the wrong well placement? The deep nwell layer should only be under drawn nwell / pwell layers and the nwell has to extend 0.4um past the end of the deep nwell on all sides (and no pwell can be within 1um or something of the end of the deep nwell)
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Manh Tran
06/02/2021, 6:17 PMthat's right, I drawn a ring of Nwell and extend 0.4um. But i think i have some problem with Nwell of some Pfets in the Well ring.
Manh Tran
06/02/2021, 6:26 PMDid you use Deep N well and sealring for your design and it pass DRC check?
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Weston Braun
06/02/2021, 6:33 PMI have a design that uses a deep nwell that passes magic DRC. I have not submitted anything through the efabless platform yet though, which is a second round DR
Weston Braun
06/02/2021, 6:34 PMI think the issue you are getting is that your individual nwells over the deep nwell are less than 4.5um apart
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Tim Edwards
06/02/2021, 6:56 PM@Manh Tran: There is some artifact being produced. I can reproduce the problem here. I'll investigate and generate a fix. It does not appear to be a real error.
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Manh Tran
06/02/2021, 7:05 PMThank you @Tim Edwards and @Weston Braun very much! So how i know that my design will pass efabless (or skywater) DRC check before submit? What another tool i can run to verify this DRC error?
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Tim Edwards
06/02/2021, 7:09 PM@Manh Tran: I will have the tech file fixed shortly; I'm a little delayed due to a couple of meetings (like sitting in on Weston Braun's presentation. . . ).
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Manh Tran
06/02/2021, 7:14 PMOh. that is nice. Thank you very much and have a nice day!
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Tim Edwards
06/04/2021, 4:34 PMI just fixed this. . . it was an incorrect rule implementation in magic where the "spacing" rule for spacing between a->b usually gets implemented in both directions (a->b and b->a). However, the "surround-ok" rule type (e.g., distance from nwell to dnwell is 4.5um except where dnwell is already surrounding nwell) is not symmetric like this, and magic wasn't prohibiting the swapped case, which then produces really weird results. But I also found that the magic tech file in open_pdks had the types for the surround-ok spacing rule in the wrong order for a couple of the rules, so I had to fix that, too. Bottom line is that this is now fixed if you update both magic and open_pdks (open_pdks you don't need to reinstall everything; just cd to the sky130 directory and run "make tools-a ; make install").