I’m working on a little project (4-bit adder with carry lookahead) to learn Magic. I’m doing it from scratch, i.e. not using standard cells or Verilog. If it turns out well, would I be able to integrate it into an Openlane project? I’d write the Verilog afterwards. Is this going about things backwards? Is hand-crafted (ok, Magic-crafted) GDS effectively a “hardened macro”?

Yes. There have been several projects on the MPW runs that were hand-crafting standard cells or cells used in a way similar to standard cells (like analog muxes and such). You might want to talk to @Philipp Gühring, who was creating standard cells using an automated system for the layout.

Perfect! Thanks! :-)

Yes, sounds like you are creating a hardened macro which can be used by Openlane. You will need a few more views (LEF, LIB, ...) and you should be able to see all those necessary things in my project: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project Let me know when you have any questions or need more documentation.