I am trying to output one signal with three different pins, but magic will show that some ports are electrically shorted and ignore some ports. Can I do this in this design or one has to use one port for one signal?

The preferred way to do this is to divide up the net using metal resistors. Replace a short length of, e.g.,

metal3

with

rmetal3

. This will show up in the netlist as a metal resistor, so it needs to be included in your schematic- or verilog-derived netlist for LVS. The other way to deal with it is to do layout extraction using

ext2spice short resistor

, which will place an ideal zero-ohm resistor between the net and each named pin.

netgen

knows how to deal with such devices (if they are in both netlists, they are compared; otherwise, if it exists in only one netlist, the device will be removed and the nets merged together).

Thanks. I will try that.

Use

res_generic_m1

. You can edit the instance of the symbol and change the model name (in the symbol properties) to whatever you want, so you can use that symbol as a stand-in for any of the metal resistors.

If I want to use res_generic in my layout, do I need to use any layer other than rmetal in the layout? Because I am running into some lvs issues, it seems that the metal res is unconnected even though I am pretty sure that the rmetal and metal are connected. Do I need a via or something like that? @Tim Edwards

@Hongzhe Jiang: The

rmetal

layer should be sufficient. Please post an example if you would like me to look at the issue.

The results are here. user_analog_project_wrapper.spice is the netlist for my schematic, user_analog_project_wrapper_empty_lvs.spice is the netlist for my layout, comp_out is the lvs result. The really weird thing is that all the nets seem to be 'misaligned' if interpreted from the lvs result. That means the two netlists have the same amount of instances and same amount of nets, but none of nets is matched.... I don't know what is happening here....

@Hongzhe Jiang: It would help if you extracted both netlists wrapped in

.subckt ... .ends

. "ext2spice lvs" will set this up automatically, and there is a netlisting option in xschem to do that. Otherwise, any issues are in the layout itself, not the netlist. The layout-extracted netlist has entries for

sky130_fd_pr__res_generic_m3

where both sides are connected to unnamed nodes. This is most likely a labeling issue, where labels are not properly attached to metal geometry in the layout, but that's just speculation since I don't have the layout.

I tried wrapping my design in a .subckt, but netgen shows 'circuit user_project_wrapper.spice contains no devices'. What should I do to configure netgen? Thanks for your help. @Tim Edwards

@Hongzhe Jiang: Use

netgen -batch lvs "file1 subckt1" "file2 subckt2" setup.tcl comp.out

.

I wrapped my design in a subckt and the netlists still did not match, but I found something weird with res_generic. From the netlist generated from my layout you can clearly see that there are 10 res_generic devices on different layers, but in the lvs result only three are counted. Moreover, some nets are missing because of the missing of devices. @Tim Edwards

Are the "UNCONNECTED_PIN" references in the schematic netlist meaningful?

I did leave some unconnected pins in the schematic, that might be the reason for the UNCONNECTED_PIN reference in the netlist.