Hi @User, I'm trying to experiment with Enclosed-Layout Transistors on SKY130 but I get plenty of DRC violations in Magic due to transistor bends and non-90-degree angles. Are these violations just to keep all transistors up to production spec or does the process physically not support them? If it's the latter, can the specific DRC errors be waived during pre-check? Thanks!

Yes, there will be errors due to transistor bends. I am implementing DRC checks following the SkyWater rules as closely as possible. However, transistor bends will not cause a layout to be rejected from fab, and there is even one SkyWater layout of an ESD transistor that has flanged ends on the gate, and so requires a DRC rule exception. There have been several designs taped out with annular transistors, so it will require testing some of these designs and getting an understanding of how reliable the layouts are; then maybe I can override the SkyWater rules, at least for selected specific annular device layouts.

Fantastic, thanks!