@User I am laying out a fingered transistor. I used a single finger nmos (without Gate contacts and guard ring) from devices1 tab, replicated it, made source/drain connections. laid out a simple Local Interconnect guard ring, added p substrate contacts on guard ring. However there were DRC errors saying ptap overlap of ptap contact <0.12um. I generated a default 1um wide nmos from devices1 menu. it has same layers but does not give a DRC error? What could I be missing ?

Paint type "psd" coincident with the local interconnect in the guard ring and it should fix the errors. The tap diffusion needs to extend past the contacts for some minimum distance.

Thanks, it worked. Now I have another query. I connected the source to guard ring. I extracted the transistor in LVS mode(ext2spice lvs). The netlist has a subcircuit which defines a 1u/0.15 nfet. But the primitive device inside it has a body terminal which is connected to VSUB. Now my source is connected to the body in the layout but in the net list S and VSUB are different. Isnt this wrong ? I have also made sure by pressing S 3 times and highlighting, that the substrate and source are connected in magic

@User I've noticed this in the more recent versions of magic, also. I just created an issue in the magic repo. https://github.com/RTimothyEdwards/magic/issues/106

I'm looking into it. There have been a number of code changes touching the extraction since version 8.3.196. If anybody can take the trouble to pin it down to a specific revision, that would be helpful.

@User I will try extracting it with all tags one by one after 196, will that help?

@User: Yes, that would be helpful. The most likely candidates are revisions 214 and 223.

8.3.214 it is. I get correct netlists till 213