I'm trying to use some deep nwells for bulk isolation, but I'm not seeing the spice netlists extracted as expected. I have two nfets, one is inside a deep nwell (bulk is tied to source), the second is outside the deep nwell with source, bulk, and ground tied together. With both fets present in the design one of them will show VSUBS incorrectly connected in the spice netlist, however, generating a netlist on just one fet at a time shows both are properly connected. I've seen @User mention in some comments that magic can't handle multiple substrate regions, but too that isosub can be used to force magic to treat different subtrate regions as separate. I tried using isosub in an island over my deep nwell, but it excludes my dnwell layer - wasn't expecting that. just tracing isosub as a perimeter didn't work either. Am I attempting to do this incorrectly? Or is this just not possible in Magic at present? Thanks

Do you have a sample layout?

I should clarify that I'm trying to pass LVS right now.

*Netlist with only the bottom nfet in the layout
.subckt dnwcell Gate2 Drain2 Source2
X0 Source2 Gate2 Drain2 Source2 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
.ends

*Netlist with only the top nfet in the layout
.subckt dnwcell Source Gate Drain
X0 Source Gate Drain Source sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
.ends

*Netlist with both nfets present
.subckt dnwcell Source Gate Drain Gate2 Drain2 Source2
X0 Source Gate Drain Source sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X1 Source2 Gate2 Drain2 VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
.ends

VSUBS in X1 is the problem. Different from the bottom nfet extracted alone

Sorry, I've been busy documenting. I'll take a look at it. Note that "isosub" should not be used with deep nwell---it is designed to keep magic's extractor from tying everything in the substrate together. The deep nwell should extract as its own net isolated from the substrate. It is possible to subvert that with complicated hierarchy (an issue with the GPIO pad layout), but I wouldn't expect that in the simple design above.

No problem! & Thanks @User My design is hierarchal, the full version of this example cell is included at a few points in my whole design. Not sure if that would be a problem or not when I extract from the top. I guess I'll wait and see if that pops up after getting this individual cell working.

@User: The quick fix here is to paint "pwell" under the transistor outside of the deep nwell, connecting together the area under the transistor and the tap diffusion. But magic should extract that correctly without needing the pwell layer drawn underneath, and I will treat that as an error and go debug it.

Great. I'll roll with the quick fix for now. Thanks! @User

@User: Thank you for the heads-up. That was a very helpful example. I just tracked down an incorrect return value deep in the extraction routines. I pushed a fix for the error (magic version 8.3.244) on opencircuitdesign.com (the github mirror site updates overnight).

@User Glad it was useful. Thanks for your work on this.