Is anybody aware with Magic VLSI doing some strang...
# magic
a
Is anybody aware with Magic VLSI doing some strange extraction for LVS for bulks of same hierarchy level cells? I am trying to extract a cell calles armleo_gpio_esd_wrapped which contains 1 transistor + 1 cell, but the transistor is placed in cell's deepnwell region, however, when doing and LVS extraction the transistor's Substrate does not match expectation: behaving the same way, as the transistor is placed in flattened design. I was expecting it to have same connection as taps near it (vssio), but instead it uses a net that is in completely irrelevant deep nwell (vss). If I just flatten the cell and then connect the transistor, it behaves correctly and substrate pin (bulk) is parsed correctly
t
Can you please post the layout?
It's essentially one layout, they are slightly different, but issue is reproducible with any design with dnwells
and cells one with dnwell (the armleo_gpio one) and one without dnwell (the armleo_gpio_ggnmos one)
the second one does not have to be a cell, but any transistor
(Commit: 4151a20670cf14a6bc3eb02a8c5364ce855eacfb)
m
You can flatten
armleo_gpio_ggnmos
virtually before extraction by using the
gds flatglob armleo_gpio_ggnmos
command.
a
That's actually a good idea, but probably I should flatten armleo_gpio, because armleo_gpio_ggnmos even flattened still causes same issue
t
@User: In the version with the commit ID that you gave above, I see cells
user_analog_project_wrapper
, which is empty,
armleo_gpio_esd_wrapped
, which has a flattened version of the cell in question, and
armleo_gpio_ggnmos$1
, which is the non-flattened cell, but doesn't appear in anything else. I'm not sure what I'm supposed to be looking at or how to reproduce the problem.
I tried extracting several different versions, and they all seem to be extracting correctly, as far as I can tell. Maybe I'm missing something.
a
bulk_issue.gds: armleo_gpio_esd_wrapped when extracted armleo_gpio_ggnmos's bulk is connected to vss instead of vssio. There is no way that it can be connected to vss, I checked everything the other gds: armleo_gpio_esd_wrapped's subcell armleo_gpio has been flattened, as a result the DNWELL is no longer in hierarchy. It's the only change, but in that case the ggnmos's bulk is correctly connected to vssio as expected
Magic 8.3.227
Hmm.. Maybe updating Magic might help. Will try that
t
I haven't changed the basic substrate extraction code since version 8.3.227, but there were a number of corrections to what ext2spice was producing that might be the problem here; that work was done around 8.3.235, so you might find that the behavior improves if you update magic.
a
Update: this solved the issue