For my latest circuit, one issue I have is that when I run ext2spice, the spice netlist is missing most of the ports from the layout. 😮 So far, I have checked that the port/labels are set to the correct layers, and that no labels are shorted together. What mistakes should I look for next? (I can upload all the files if anyone had the time to take a look...)

Yes, just upload the .mag file(s) and explain what the ports are supposed to look like in the output.

I appreciate it! thanks! The port of SSTL should be: pu_cal_ctrl[0:3], pd_cal_ctrl[0:3], pu_ctrl[0:6], pd_ctrl[0:6], DQ, VDD, GND

This has to do with labels that are on the top level, have no width to the label rectangle, and no material directly under the label (the label is on the edge of the material). There is an option "extract do labelcheck" that is supposed to make this work, but for some reason it's not. I will debug this; however, if you don't want to wait for my fix, you can just make the labels a proper rectangle and fill that rectangle with the connecting material on the top level layout. That should work around the issue.

So I have made the labels/ports into rectangles. However, this had no effect on the output spice netlist. But I have a new guess about the issue: it looks like many ports have the same "index". This is a mistake right? I think so because only one port per index shows up in the final netlist. I think this happened when I created ports by copying other ports, and changed the names after.

Ah, I didn't notice that the port indexes were the same. . . That should have been immediately apparent to me! Sorry for missing that, or I could have saved you a bit of trouble debugging. But thanks for the update.