Derek Hines-Mohrman
02/13/2022, 11:10 PMextract all
), it looks like no parasitic resistances are extracted. I am checking this by reading the resulting .ext
file.
Is there some additional setting I need to set?
This happens in every example I have tested, but here I included my specific example. I open SSTL.mag, and run select top cell; extract all
.
Are there really no significant parasitic resistances in this design?Arman Avetisyan
02/14/2022, 3:36 AMArman Avetisyan
02/14/2022, 3:38 AMHarald Pretl
02/14/2022, 11:04 AMTim Edwards
02/14/2022, 1:34 PMflatten cellname_flat
load cellname_flat
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice
A couple of notes: (1) extresist
does not work well with hierarchy. Your best bet is to flatten the circuit before running parasitic extraction. The flatten cellname_flat
command flattens the loaded cell and places it into a new cell called cellname_flat
. This will make the top level subcircuit in the output called `cellname_flat`; there are ways to work around that but probably not worth worrying about. (2) I always like to use ext2spice lvs
even when not doing LVS because it sets "sane" configuration; then I redo some settings like the capacitance threshold, for parasitic extraction.Derek Hines-Mohrman
02/15/2022, 12:28 AMset NAME [cellname list self];
select top cell;
# (Flattening improves resistance extraction)
flatten "[list $NAME]_flat"
load "[list $NAME]_flat"
select top cell;
extract do resistance;
extract all;
ext2sim labels on;
ext2sim;
extresist tolerance 10;
extresist all;
ext2spice lvs;
ext2spice cthresh 0;
ext2spice extresist on;
ext2spice -o "pex_[list $NAME].spice";