This is supposedly a valid nmos transistor bin: sky130_fd_pr__nfet_01v8 52 0.36 0.15 However, you can't draw a 0.36 wide transistor without getting this error: Transistor width < 0.42um (diff/tap.2) Is there a way to draw this?

Maybe there is a marking layer required to allow this small MOST size?

@User: Use the devices "scnmos", "scpmos", and "scpmoshvt". In magic, if you want a layer to have different DRC rules, then you need a different tile type to represent it (which is why there are various different layers and devices related to the SRAM). I looked at all the standard cell sets and determined that the three device types I listed are the only ones that appear in standard cells, and so (in theory, anyway) the only ones for which the 0.36 width is allowed. Use of the device type also causes the standard cell ID layer (

<http://areaid.sc|areaid.sc>

) to be generated over the cell, which should keep other DRC engines (e.g., klayout) happy.