Hi, I'm slowly getting desparate on LVS. My design consists of a reference current source, a TIA and an 50 Ohm output driver. For the reference current source I managed to get the design LVS clean by not using hierarchy for many parts and slowly assemling the design so that magic would always be able to extract it. For the TIA I now used hierarchy and again cannot extract the spice file. What I'm doing ist: • Select all subcells and issue

select flat ; select keep

•

extract all; ext2spice hierarchy off; ext2spice scale off; ext2spice cthresh infinite; ext2spice

So far I tested magic in versions 8.3.268, 8.3.270, 8.3.272, 8.3.274, 8.3.275. None seems to work. What version of magic are you using? How do you solve the LVS issue? The deadline for MPW-5 submission is approaching, my design would be ready, but submitting without LVS is a bit pointless.

@User That's some crazy spice file. I haven't done LVS on magic files directly, but after importing from GDS, these are the commands that I would use to extract a hierarchical spice file.

load tia_core
extract unique
extract
ext2spice lvs
ext2spice

I've seen problems with extraction of parameterized cells, so I flatten those before extracting. (This is trivial when importing from GDS). Check out this thread about permanently flattening subcells in magic. https://skywater-pdk.slack.com/archives/C016YSAP6TZ/p1644998694479219 Let me know how it goes. I might have some other ideas if the above doesn't work.

@User: Can you post the netlist against which you are trying to do LVS?

@User Sure, here is the netlist

Ah.

select cell

is not supposed to be done on the top level cell; it's supposed to be done on a subcell; that is, the correct invocation would be

select top cell ; unexpand ; select area subcell

. That is, you didn't actually do what you said above you were doing, which was to "select all subcells". But I can confirm that

select pick

does very weird and unfortunate things when applied to the top-level cell, which is something I need to prevent magic from doing.

Ok, I now got the posted circuit LVS clean. In the next circuit I'm now again facing a magic bug preventing the extraction of the bulk connection. I posted it here: https://github.com/RTimothyEdwards/magic/issues/136

I saw the issue and am working on it.

Thank you very much!

@User: Good, because I'm buried in a number of things that all manage to have topmost priority at the same time. I still have your layout up in a window on my desktop and will get back to it after things settle down a bit.