I thought that the The foundry bitcell is single port only, and the OpenRAM designed bit cell is dual port only

All the bitcells are foundry bitcells.

Ah, ok

Ah I was hoping for 1W+2R configs, but I guess that would need a 3 port cells from the foundry.

Yeah, there is nothing for that right now. Nothing stops us from making a "user rules" bitcell though.

Sure. Do you have metrics as how smaller it is vs something you can make within user DRC rules ?

No, but my gut is probably 10-20% bigger

ok, so not the end of the world. Would still be way better than having to instanciate 2 SRAM blocks in 1RW+1R to emulate 1W+2R.

And using DFFs is like 4-5x bigger

That's something else I wanted to measure / check. I'm assuming that for "small" memories, FFs could actually be viable right (because SRAM has some overhead IIUC)? But I'm not sure what "small" is in this context.

Yeah, the intercept is in the ballpark of 100-300 bits IIRC?

Oh wow, that's much lower than I thought.

You can also make a latch-based register file which is more efficient than a DFF one

Yeah, using latches was on my list to look into as well. Excatly for stuff like register files, or tiny FIFOs .

If you make a parameterized Verilog model send it my way and I can get a student sometime to work on the scripted layout

I'll keep that in mind !

I've put that as a project in my class for a couple years now but nobody selects it 😞