<@U0175T39732> Is there a way to have R, R, W port...
# openramt
Tim 'mithro' Ansell
08/03/2020, 11:15 PM
@User Is there a way to have R, R, W ports? IE Two independent read ports and third independent write port?
m
Matthew Guthaus
08/03/2020, 11:26 PMNo. There are two barriers to that right now:
1. No bitcell. We could make our own.
2. We only support 2 ports (of any kind) in the SRAM floorplan right now. A third port would need to either interleave somehow or use higher metal layers to route it.
It sounds like what you want is a register file. This would use a different bitcell entirely and would also have different read ports (probably not a sense amp?)
Matthew Guthaus
08/03/2020, 11:27 PMMy suggestion for this is that we can make a latch-based register file within the OpenRAM infrastructure. It would use the standard cell latch and create the addressing logic with standard cells using a regular placement.
Matthew Guthaus
08/03/2020, 11:27 PMOr, you could place it as cells too.
t
tnt
08/04/2020, 6:01 AMYup doing it with latches and integrating it in the normal cell grid is what I started looking into.
tnt
08/04/2020, 6:02 AMAlso why I was asking about the bit cell area to get an idea of how big that'd be compared to an SRAM cell based solution.
m
Matthew Guthaus
08/04/2020, 2:32 PMLatches are about half of a DFF so they are much closer. Maybe 2-3x bigger than the dual port cell rather than 4-5x
t
Tim Edwards
08/04/2020, 8:26 PM@Tim 'mithro' Ansell: Any particular reason for the R/R/W configuration? The PicoRV32 uses this for its register file. But a register file usually has a slightly different configuration than an SRAM.
Tim Edwards
08/04/2020, 8:28 PM@Tim 'mithro' Ansell: For the picoRV32 implementations, I just synthesized the register file. For the limited number of flops in a register file, you don't get that much of an overhead impact from synthesizing. Of course, it does depend on the number of registers.
t
tnt
08/04/2020, 8:28 PMPretty sure it's for a reg file 🙂 In FPGA it's just common to use the same block ram for that as well, and as a fpga guy, using SRAM for that was my first reflex too ...
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