Is that liberty file somewhere ? I don't see it in...
# openramt
tnt
11/14/2020, 6:22 PMIs that liberty file somewhere ? I don't see it in the caravel or openlane.
m
Matthew Guthaus
11/14/2020, 6:31 PMThe liberty file has uncalibrated analytical models for delay, so it is literally junk.
Matthew Guthaus
11/14/2020, 6:31 PMIf you want it solely for pin names etc I can give it to you
Matthew Guthaus
11/14/2020, 6:32 PMThe setup time will be similar to the OSU cell library DDF.
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tnt
11/14/2020, 6:40 PMOk. And if I remember correctly, for write, all inputs are samples on rising edge and for read, the address is sampled on rising edge, then during the clock high period it's used for precharge and then on the falling edge the data will actually be output. Is that correct ?
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Matthew Guthaus
11/14/2020, 7:23 PMData will be output some time after the falling edge, yes. By the next rising edge.
👍 1
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tnt
11/14/2020, 9:02 PMOh wait the WRITE port uses the negative edge ? ( reading
sram_1rw1r_32_256_8_sky130tnt
11/14/2020, 9:03 PMNevermind, it does the write to the cell onthe neg edge but using addr/data captured on the rising edge.
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Matthew Guthaus
11/14/2020, 10:40 PMYes
a
Ahmed Ghazy
11/18/2020, 5:04 PM@Anish ^
a
Anish
11/18/2020, 6:11 PMwould it work at ~100mhz or would it be better at closer to 50?
Anish
11/18/2020, 6:17 PM(assuming both address and output are registered - or is there a simulation/spice setup somewhere I can test it with?)
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Matthew Guthaus
11/18/2020, 8:40 PM@Anish I would say closer to 50, but we haven't tested real silicon yet
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tnt
11/18/2020, 8:41 PM😕 That's not boding well for me. I need to run at 48 MHz (sort of required for USB ...) but I don't have the whole cycle to dedicate to the RAM requirement, there is logic to/from inputs/outputs.