Any suggestions or tips on creating tech.py and drc files for open ram sky130 ? Also master openram compiler giving drc issues on auto generated cells like precharge etc.. shall I need to work with openram dev version to resolve such issues? Thanks in advance . Suggest if my tech.py file is correct or needs corrections. Find the file at https://github.com/pradeepsk13/vsdsram_sky130_1.8V/blob/main/Openram/sky130A/tech/tech.py

I really should make what I have public and am working on that right now. I have it working minus a few supply routing issues. I'm not sure about your question about the generated cells -- I would need to see a test case.

Decoder circuits , precharge circuit are generated from open ram compiler have contacts drc issues . I have addressed drc issues of bitcell, senseamp and write driver for now. I thought my tech.py is not complete which might be reason for issues from compiler while generating other cells.

If these are with your own tech file then there is likely a problem with that. It is quite a bit of work to get it right.

Yes its own tech file , have confusions example grid value , viali ,mcon.etc