Pushed some new macros that are closer to final. P...
# openramm
Matthew Guthaus
05/30/2021, 8:01 PMPushed some new macros that are closer to final. Power routing and d well updates as well as supply names to with with pdngen/OpenLane
https://github.com/efabless/sky130_sram_macros
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Matthew Guthaus
05/30/2021, 8:02 PM8kbyte still needs some more verification.
LVS issue has a few simple fixes due to devices in the bit cell being extracted differently with the updated PDK tech files
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Sajjad Ahmed
05/30/2021, 11:44 PMHi @Matthew Guthaus !
Should we go for 8kb model Or 4kb model is fixed use??
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Matthew Guthaus
05/30/2021, 11:46 PMThese are all preliminary, but the 4kb is more confident than the 8kb. I will likely need to use local wordlines in the 8kb which may change the size. They will all be updated periodically until we get to tape out.
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Olof Kindgren
05/31/2021, 6:46 AMAwesome! There's an 8-bit version now I see!
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Nikhil Poole
06/12/2021, 6:28 PM@Matthew Guthaus I'm currently working on a mixed-signal chip and my digital section uses a few of the 8KB SRAMs. My tapeout is next week, and I just wanted to verify that these are good to use, i.e. DRC/LVS clean (I'm using Magic and netgen). Worst comes to worst, I can string together multiple smaller SRAMS but would prefer not to if possible. If you're not confident in the 8KB SRAM, what would you say is the largest one that I can use in my design? Thanks in advance! I really appreciate your help!
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Matthew Guthaus
06/12/2021, 9:03 PMI would suggest the 2kb or 4kb. The smaller ones have more verification. There are a couple small issues but they will be DRC/LVS clean by then. They take a while to generate and check.
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Nikhil Poole
06/12/2021, 9:20 PMGotcha, thanks! I'll string together a couple 4KB macros for each 8KB SRAM then.
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