open-source-silicon.dev

image.png

<@U0175T39732> I get these errors around SRAM boundary, usually when it connects them to IOs
 `Metal4 &gt; 3um spacing to unrelated m4 &lt; 0.4um (met4.5b)`
I have these errors on metal 1 metal 2 metal 3 and metal 4.
All of them have one thing in common that they are at the boundary of SRAM
Have I missed something during PnR, any setting I should be aware of?

You can create routing blockage so that the router will not use these areas. This is mine in config.tcl:
```set ::env(GLB_RT_OBS) "met4 486.975 904.22 487.305 904.225, met4 303.895 904.22 304.225 904.225"```

Triton route doesn't respect the wide metal spacing associated with the blockages.

<@U0223CL4ASY> is that a box around the hole memory or a particular area where it happened?

It is a particular area where the violations happened. There are two on metal 4 in my design as in the example above.

I see. That may be too hunt and peck for a general solutiom

drc-vio-2-20210629.png

OpenRoad created some routes which are quite weird to me. This is one of the violations in my design.

Yeah, it looks like it isn't blocking that horizontal track and it should. The via causes a spacing issue but not the wire.

I have around 400 such warnings. What should I do in this case?
<@U0175T39732> <@U0223CL4ASY>

I'm not sure how efabless will want to handle this. It's not really a DRC error since the blockages are the entire memory size and nothing is near the perimeter.

The better solution is to get someone to file an issue with TritonRoute and see if there's a fix

These routes are from Innovus-Cadence. If TritonRoute is also behaving that way then I think something else is going wrong here for both the routers to behave peculiarly

<@U016Y9FMA2Y> Are your violations similar to mine? If it is true, you can create the routing blockage in Innovus. As far as I remembered, changing the floorplan can also help. You can find a better floorplan so that routing to the SRAM ports is easier and can avoid violations.

<@U016Y9FMA2Y> hmm, yes, that is interesting. Though it's just a lef file with blockage shapes so I'm not sure what could be wrong...

<@U016Y9FMA2Y> does cadence-innovus have the wide metal rules? It could be a bug in that technology config then

<@U0175T39732> Umm I am not sure about that.
What's wide metal rule ?
I don't see anything of the sort in the techlef file though.
With what name is it defined in techlef?

In the design rules, it is:
(m4.5b) Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a 0.400µm

The DRC probably infers the blockage as huge_metX, but the router doesn't

and huge_metX spacing is greater than metX spacing

Aah so its like that..
I would look into it and let you know if I find anything

<@U0175T39732> yes, the spacingtable in the .tlef file defines spacing for different metal widths. e.g.
…
LAYER met4
 TYPE ROUTING ;
 DIRECTION VERTICAL ;

 PITCH 0.92 ;
 OFFSET 0.46 ;

 WIDTH 0.3 ;       # Met4 1
 # SPACING 0.3 ;       # Met4 2
 SPACINGTABLE
   PARALLELRUNLENGTH 0
   WIDTH 0 0.3
   WIDTH 3 0.4 ;
 AREA 0.24 ;      # Met4 4a
…